EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 668

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

21
21-12
I
EP93xx User’s Guide
21.7.1 I
21.7 Registers
2
S Controller
Table 21-7
addressable. The left and right data registers for channels 0, 1 and 2 can be accessed by
both APB and DMA accesses. The remaining registers are concerned with control / status
information and can be only accessed through the APB bus.
2
S TX Registers
0x8082_001C
0x8082_002C
0x8082_003C
0x8082_0010
0x8082_0014
0x8082_0018
0x8082_0020
0x8082_0024
0x8082_0028
0x8082_0030
0x8082_0034
0x8082_0038
Address
summarizes the register set in the Transmitter. Each of the registers listed are
FIFO underflow
FIFO overflow
FIFO empty
FIFO Flag
FIFO full
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Width
32
32
32
32
32
32
3
2
2
1
1
1
Copyright 2007 Cirrus Logic
Reset
Value
Table 21-7. I
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Table 21-6. FIFO Flags
Interrupt and status bit
Interrupt and status bit
Transmitter
I2STXLinCtrlData
I2STXWrdLen
Sticky bit
I2STX0En
I2STX1En
I2STX2En
I2STX0Lft
I2STX1Lft
I2STX2Lft
Status
I2STX0Rt
I2STX1Rt
I2STX2Rt
I2STXCtrl
2
Name
S TX Registers
Left Transmit data register for channel 0
Right Transmit data register for channel 0
Left Transmit data register for channel 1
Right Transmit data register for channel 1
Left Transmit data register for channel 2
Right Transmit data register for channel 2
Line Control data register
Control register
Word Length
TX0 Channel Enable
TX1 Channel Enable
TX2 Channel Enable
Interrupt and status bit
Interrupt and status bit
Description
Receiver
Status bit.
Sticky bit
DS785UM1