EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 580

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

16
UART3RXSts
16-4
UART3 With HDLC Encoder
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808E_0004 - Read/Write
0x0000_0000
UART3 Receive Status Register and Error Clear Register. Provides receive
status of the data value last read from the UART3Data. A write to this register
clears the framing, parity, break and overrun errors. The data value is not
important.
RSVD:
OE:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
a 3-bit status (break, frame and parity) is pushed onto the
11-bit wide receive FIFO
• if the FIFOs are not enabled, the data byte and status are
stored in the receiving holding register (the bottom word of
the receive FIFO).
The received data byte is read by performing reads from
the UART3Data register, while the corresponding status
information can be read by a successive read of the
UART3RXSts register.
Reserved. Unknown During Read.
Overrun Error.
1 - when data is received and the FIFO is already full.
0 - Cleared by a write to UART3RXSts.
The FIFO contents remain valid since no further data is
written when the FIFO is full. Only the contents of the shift
register are overwritten. The data must be read in order to
empty the FIFO.
24
8
RSVD
23
7
22
6
21
5
20
4
OE
19
3
BE
18
2
PE
17
1
DS785UM1
FE
16
0