EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 493

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

PCIO
DS785UM1
31
WI
15
Address: 0x8008_0028 - Read/Write
Default: 0x0000_0000
Definition: PC Card IO register
Bit Descriptions:
30
14
RSVD
29
13
28
12
HC:
PC:
RSVD:
WI:
RSVD
27
11
26
10
HI
Copyright 2007 Cirrus Logic
25
9
The value written to this field specifies the minimum
‘number of HCLK cycles, minus 1’ that the data strobe,
MCDAENn
The data strobe assertion time is specified by (AC+1)
HCLK cycles. For example, if AC = 0x10, the data strobe
assertion time is 16 + 1 = 17 cycles of HCLK
Common space Hold time - Read/Write
The value written to this field specifies the minimum
‘number of HCLK cycles, minus 1’ between de-asserting
the data strobe, MCDAENn
strobe, MCADENn.
The Hold time is specified by (HC +1) HCLK cycles. For
example, if HC = 0xC, the Hold time is 12 + 1 = 13 cycles
of HCLK.
Common space setup time - Read/Write
The value written to this field specifies the ‘number of
HCLK cycles, minus 1’ that the address strobe,
MCADENn, is set up before assertion of the data strobe,
MCDAENn.
The Setup time is specified by (PC+1) HCLK cycles. For
example, if PC = 0x25, the Setup time is 37 + 1 = 38
cycles of HCLK.
Reserved - Unknown During Read
IO Space Width - Read/Write
The value written to this bit specifies the bus-width of the
IO space:
24
8
,
23
7
is asserted during a Read or Write access.
22
6
21
5
,
and de-asserting the address
20
4
AI
PI
19
Static Memory Controller
3
EP93xx User’s Guide
18
2
17
1
12-15
16
0
12