EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 309

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
9.1.4 Transmit Back-Off
9.1.4.1 Transmission
9.1.4.2 The FCS Field
Refer to
there is a collision. There are two kinds of collision: normal collision (one that occurs within
the first 512 bits of the packet) and late collision (one that occurs after the first 512 bits). In
either collision type, the MAC engine always sends a 32 bit jam sequence, and stops
transmission.
After a normal collision and the jam, transmission is stopped, or “backed-off”. The MAC
attempts transmission again according to one of two algorithms. The ISO/IEC standard
algorithm or a modified back-off algorithm may be used, and the host chooses which
algorithm through the ModBackoffE control bit (TXCtl). The standard algorithm from ISO/IEC
paragraph 4.2.3.2.5 is called the “truncated binary exponential backoff” and is shown below:
where r is a random integer for the number of slot times the MAC waits before attempting
another transmission, and a slot time is time of 512 bits (51.2 μsec), k = minimum (n,10), and
n is the nth retransmission attempt. The modified back-off algorithm uses delays longer than
the ISO/IEC standard after each of the first three transmit collisions as shown below:
where k = minimum (n,10), but not less than 3, and n is the nth retransmission attempt
The advantage of the modified algorithm over the standard algorithm is that the modification
reduces the possibility of multiple collisions on any transmission attempt. The disadvantage is
that the modification extends the maximum time needed to acquire access to the medium.
The host may choose to disable the back-off algorithm altogether. This is done through the
control bit DisableBackoff (TestCtl). When set, the MAC transmitter waits for the Inter Frame
Gap time before starting transmission. There is no back-off algorithm employed. When clear,
the MAC uses either the standard or the modified algorithm.
After the transmission has passed the time for a normal collision (512 bits), then transmission
is either completed, or aborted due to a late collision. For a late collision, the transmitter
sends the 32 bit jam sequence, but does not back-off and try again. When a late collision
occurs, Out-of-wdw collision (XStatQ) is set. A late collision is not retried, because the first 64
bytes of the FIFO are freed after the normal collision window, and will likely be refilled by a
following packet. Driver intervention is needed to reconstruct the FIFO data.
If InhibitCRC (Transmit Descriptor) is clear, the MAC automatically appends the standard 32
bit FCS to the end of the frame. The MAC tests the last 32 bits received against the standard
CRC computation. If received in error, CRCerror (RStatQ) is set. If CRCerroriE (Interrupt
Enable) is set, there is an interrupt associated with CRCerror. The standard CRC conforms to
ISO/IEC 8802-3 section 3.2.8. The polynomial for the CRC is:
G(x) = x
32
Figure
+ x
26
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9-3. Once transmission is started, either the transmission is completed, or
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16
Copyright 2007 Cirrus Logic
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0 <= r <= 2
0 <= r <= 2
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k
k
10
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1/10/100 Mbps Ethernet LAN Controller
5
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EP93xx User’s Guide
9-7
9