EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 225
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9302-CQZ
Manufacturer:
Cirrus
Quantity:
3 295
Company:
Part Number:
EP9302-CQZ
Manufacturer:
ALTERA
Quantity:
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Part Number:
EP9302-CQZ
Manufacturer:
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- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 225 of 824
- Download datasheet (13Mb)
HActiveStrtStop
DS785UM1
31
15
Address: 0x8003_0018
Default: 0x0000_0000
Definition: Horizontal Active period Start/Stop register
Bit Descriptions:
Note: When horizontal clock gating is required, set the STRT and STOP fields in the
30
14
RSVD
RSVD
HActiveStrtStop register to the STRT and STOP values in HClkStrtStop + 5. This is a
programming requirement that is easily overlooked.
29
13
28
12
RSVD:
STOP:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
The STOP value is the horizontal down counter value at
which the HSYNCn signal becomes inactive (stops). When
the Horizontal counter counts down to the STOP value,
the HSYNCn signal goes inactive. Please refer to video
signalling timing diagrams in
STRT:Start - Read/Write
The STRT value is the horizontal down counter value at
which the HSYNCn signal becomes active (starts). When
the Horizontal counter counts down to the STRT value, the
HSYNCn signal goes active (starts). Please refer to video
signalling timing diagrams in
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HACTIVE signal becomes inactive
(stops). This indicates the end of the active video portion
for the Horizontal line. Please refer to video signalling
timing diagrams in
is an internal block signal. The active video interval is
controlled by the logical OR of VACTIVE and HACTIVE.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
23
7
22
6
Figure 7-9
STOP
STRT
21
5
Figure 7-9
Figure 7-9
20
and
4
Figure
19
3
EP93xx User’s Guide
and
and
7-10. HACTIVE
18
2
Figure
Figure
17
1
7-10.
7-10.
16
7-43
0
7
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