EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 516

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

13
RefrshTimr
13-20
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User’s Guide
31
15
Address: 0x8006_0008 - Read/Write
Default: 0x0000_0080
30
14
Initialize
1
1
0
0
0
1
1
0
29
13
28
12
MRS
1
0
1
1
0
0
1
0
Table 13-14. Synchronous Memory Command Encoding
27
11
LCR
0
0
0
1
1
1
1
0
26
10
Issue NOP to Synchronous Memory
Issue PreALL (Pre-charge All) to SDRAM
Enable access to Synchronous Memory device mode register
Issue command to Synchronous FLASH Memory devices
UNDEFINED. Do not use.
UNDEFINED. Do not use.
UNDEFINED. Do not use.
Normal operation
Copyright 2007 Cirrus Logic
25
9
Writing a ‘1’ to this bit, in combination with the values of
the MRS and LCR bits, cause the Synchronous Memory
controller to issue either NOP or PreALL accesses to
SDRAM devices as shown in
0 - See
1 - See
24
Synchronous Memory Command
8
Refcnt
RSVD
Table 13-14
Table 13-14
23
7
22
6
21
5
Table
20
4
13-4.
19
3
18
2
17
1
DS785UM1
16
0