EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 241
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9302-CQZ
Manufacturer:
Cirrus
Quantity:
3 295
Company:
Part Number:
EP9302-CQZ
Manufacturer:
ALTERA
Quantity:
672
Part Number:
EP9302-CQZ
Manufacturer:
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Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 241 of 824
- Download datasheet (13Mb)
DS785UM1
S:
P:
M3
S2
P2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
Table 7-14. Blink Mode Definition Table (Continued)
M2
S1
1
1
1
1
1
1
1
P1
0
0
1
1
0
0
1
1
0
0
1
1
Table 7-16. Bits per Pixel Scanned Out
Table 7-15. Output Shift Mode Table
M1
0
1
1
0
0
1
1
Copyright 2007 Cirrus Logic
S0
P0
0
1
0
1
0
1
0
1
0
1
0
1
Shift - Read/Write
The Shift Mode is specified by selecting a value from
Table 7-15
Pixel - Read/Write
The number of bits per pixel that are output on the P[x]
pins is specified by selecting a value from
writing it to this field.
The Graphics Engine has a separate setting for this value,
which may or may not be the same.
M0
Raster Engine With Analog/LCD Integrated Timing and Interface
1
0
1
0
1
0
1
Dual Scan 2 2/3 3-bit pixels per clock over 8-bit bus
2 - pixels per shift clock (up to 9 bits wide each)
4 - pixels per shift clock (up to 4 bits wide each)
8 - pixels per shift clock (up to 2 bits wide each)
Undefined - Defaults to 1 - pixel per pixel clock
1 - pixel mapped to 18 bits each pixel clock
1 - pixel per pixel clock (up to 24 bits wide)
2 2/3 3-bit pixels per clock over 8 bit bus
Blink to offset color 888 mode (555,565)
Blink to offset color single value mode
and writing it to this field.
pixel multiplexer disabled
Blink brighter 888 mode (555,565)
Blink dimmer 888 mode (555,565)
Blink dimmer single value mode
Blink brighter single value mode
4 bits per pixel
8 bits per pixel
Pixel Mode
Shift Mode
do not use
Blink Mode
Undefined
EP93xx User’s Guide
Table 7-16
and
7-59
7
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