ATMEGA32U4-AU Atmel, ATMEGA32U4-AU Datasheet - Page 136

• Manufacturer Part Number: ATMEGA32U4-AU
• Description: MCU AVR 32K FLASH 16MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U4-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: SPI/TWI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 2.5KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 26
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2.5KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA32U4-16AU; ATMEGA32U4-16AU

14.10.17 Timer/Counter1 Interrupt Mask Register – TIMSK1
14.10.18 Timer/Counter3 Interrupt Mask Register – TIMSK3
14.10.19 Timer/Counter1 Interrupt Flag Register – TIFR1
7766F–AVR–11/10
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
R
7
–
R
0
7
–
0
7
–
R
0
(See “Interrupts” on page
(See “Interrupts” on page
(See “Interrupts” on page
6
–
R
0
6
–
R
0
6
–
R
0
61.) is executed when the TOVn Flag, located in TIFRn, is set.
5
ICF1
R/W
0
5
ICIE1
R/W
0
5
ICIE3
R/W
0
61.) is executed when the ICFn Flag, located in TIFRn, is set.
4
–
R
0
4
–
R
0
R
4
–
0
61.) is executed when the OCFnC Flag, located in
61.) is executed when the OCFnB Flag, located in
61.) is executed when the OCFnA Flag, located in
3
OCF1C
R/W
0
3
OCIE1C
R/W
0
3
OCIE3C
R/W
0
2
OCF1B
R/W
0
2
OCIE1B
R/W
0
2
OCIE3B
R/W
0
1
OCF1A
R/W
0
1
OCIE1A
R/W
0
ATmega16/32U4
1
OCIE3A
R/W
0
0
TOV1
R/W
0
0
TOIE1
R/W
0
0
TOIE3
R/W
0
TIFR1
TIMSK1
TIMSK3
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