ATMEGA32U4-AU Atmel, ATMEGA32U4-AU Datasheet - Page 282

• Manufacturer Part Number: ATMEGA32U4-AU
• Description: MCU AVR 32K FLASH 16MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U4-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: SPI/TWI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 2.5KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 26
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2.5KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA32U4-16AU; ATMEGA32U4-16AU

7766F–AVR–11/10
Then, clear by software to complete the reset operation and start using the endpoint.
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 - STALLRQ - STALL Request Handshake Bit
Set to request a STALL answer to the host for the next handshake.
Cleared by hardware when a new SETUP is received. Clearing by software has no effect.
See Section 22.11, page 270 for more details.
• 4 - STALLRQC - STALL Request Clear Handshake Bit
Set to disable the STALL handshake mechanism.
Cleared by hardware immediately after the set. Clearing by software has no effect.
See Section 22.11, page 270 for more details.
3
• RSTDT - Reset Data Toggle Bit
Set to automatically clear the data toggle sequence:
For OUT endpoint: the next received packet will have the data toggle 0.
For IN endpoint: the next packet to be sent will have the data toggle 0.
Cleared by hardware instantaneously. The firmware does not have to wait that the bit is cleared.
Clearing by software has no effect.
• 2 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 - EPEN - Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall always be
enabled after a hardware or USB reset and participate in the device configuration.
Clear this bit to disable the endpoint. See Section 22.6, page 267 for more details.
• 7-6 - EPTYPE1:0 - Endpoint Type Bits
Set this bit according to the endpoint configuration:
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R
7
0
7
0
-
EPTYPE1:0
R/W
R
6
0
-
6
0
STALLRQ
W
5
0
R
5
0
-
STALLRQC
R
W
4
0
-
4
0
RSTDT
R
3
0
-
W
3
0
R
2
0
ATmega16/32U4
-
2
R
0
-
R
1
0
-
R
1
0
-
EPDIR
R/W
EPEN
R/W
0
0
0
0
UECFG0X
UECONX
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