AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 124

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.4.7
14.5
32059J–12/2010
Flash commands
Writing words to a page that is not completely erased
The page buffer is also used for writes to the User page.
Write operations can be prevented by programming the Memory Protection Unit of the CPU.
Writing 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable data
corruption.
Page buffer write operations are performed with 4 wait states.
Writing to the page buffer can only change page buffer bits from one to zero, i.e. writing
0xaaaaaaaa to a page buffer location that has the value 0x00000000, will not change the page
buffer value. The only way to change a bit from zero to one, is to reset the entire page buffer with
the Clear Page Buffer command.
The page buffer is not automatically reset after a page write. The programmer should do this
manually by issuing the Clear Page Buffer flash command. This can be done after a page write,
or before the page buffer is loaded with data to be stored to the flash page.
Example: Writing a word into word address 130 of a flash with 128 words in the page buffer.
PAGEN will be updated with the value 1, and the word will be written into word 2 in the page
buffer.
This can be used for EEPROM emulation, i.e. writes with granularity of one word instead of an
entire page. Only words that are in an completely erased state (0xFFFFFFFF) can be changed.
The procedure is as follows:
1. Clear page buffer
2. Write to the page buffer the result of the logical bitwise AND operation between the con-
3. Write Page.
The FLASHC offers a command set to manage programming of the flash memory, locking and
unlocking of regions, and full flash erasing. See chapter 14.8.2 for a complete list of commands.
To run a command, the field FCMD.CMD has to be written with the command number. As soon
as FCMD is written, the FRDY bit is automatically cleared. Once the current command is com-
plete, the FRDY bit is automatically set. If an interrupt has been enabled by setting the bit FRDY
in FCR, the interrupt line of the flash controller is activated. All flash commands except for Quick
Page Read (QPR) will generate an interrupt request upon completion if FRDY is set.
After a command has been written to FCMD, the programming algorithm should wait until the
command has been executed before attempting to read instructions or data from the flash or
writing to the page buffer, as the flash will be busy. The waiting can be performed either by poll-
ing the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The command
written to FCMD is initiated on the first clock cycle where the HSB bus interface in FLASHC is
IDLE. The user must make sure that the access pattern to the FLASHC HSB interface contains
an IDLE cycle so that the command is allowed to start. Make sure that no bus masters such as
DMA controllers are performing endless burst transfers from the flash. Also, make sure that the
CPU does not perform endless burst transfers from flash. This is done by letting the CPU enter
sleep mode after writing to FCMD, or by polling FSR for command completion. This polling will
result in an access pattern with IDLE HSB cycles.
tents of the flash page and the new data to write. Only words that were in an erased state
can be changed from the original page.
AT32UC3B
124