AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 284

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• DATNB: Data Number per Frame
• MSBF: Most Significant Bit First
• LOOP: Loop Mode
• DATLEN: Data Length
32059J–12/2010
DATLEN
Others
8-15
The pulse length is equal to ({FSLENHI,FSLEN} + 1) receive clock periods. Thus, if {FSLENHI,FSLEN} is zero, the Receive
Frame Sync signal is generated during one receive clock period.
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
1: The most significant bit of the data register is sampled first in the bit stream.
0: The lowest significant bit of the data register is sampled first in the bit stream.
1: RX_DATA is driven by TX_DATA, RX_FRAME_SYNC is driven by TX_FRAME_SYNC and TX_CLOCK drives RX_CLOCK.
0: Normal operating mode.
The bit stream contains (DATLEN + 1) data bits.
This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the receiver.
1-7
0
Transfer Size
Forbidden value
Data transfer are in bytes
Data transfer are in halfwords
Data transfer are in words
AT32UC3B
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