AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 240

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.13.4.2
19.13.4.3
19.13.4.4
19.13.4.5
19.13.5
19.13.5.1
32059J–12/2010
Data Transfer
Write Sequence
Clock Synchronization Sequence
General Call
Peripheral DMA Controller
Read Operation
As soon as data is written in the THR, TXRDY (Transmit Holding Register Ready) flag is reset,
and it is set when the shift register is empty and the sent data acknowledged or not. If the data is
not acknowledged, the NACK flag is set.
Note that a STOP or a repeated START always follows a NACK.
See
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register
Ready) flag is set as soon as a character has been received in the RHR (TWI Receive Holding
Register). RXRDY is reset when reading the RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address dif-
ferent from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set
and SVACC reset.
See
In the case where THR or RHR is not written/read in time, TWI performs a clock synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL
and to decode the new address programming sequence.
See
As it is impossible to know the exact number of data to receive/send, the use of Peripheral DMA
Controller is NOT recommended in SLAVE mode.
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address
starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direc-
tion of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded
in the THR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 19-24 on page 241
Figure 19-24 on page
Figure 19-25 on page
Figure 19-27 on page 243
Figure 19-26 on page
describes the write operation.
241.
241.
242.
and
Figure 19-28 on page
244.
AT32UC3B
240