AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 390

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

32059J–12/2010
RXOUTI
FIFOCON
RXOUTI
FIFOCON
OUT
OUT
•Detailed description
(bank 0)
(bank 0)
DATA
DATA
Figure 22-20. Example of an OUT Endpoint with one Data Bank
Figure 22-21. Example of an OUT Endpoint with two Data Banks
The data is read, following the next flow:
• When the bank is full, RXOUTI and FIFOCON are set, what triggers an EPnINT interrupt if
• The user acknowledges the interrupt by writing a one to RXOUTIC in order to clear RXOUTI.
• The user can read the byte count of the current bank from BYCT to know how many bytes to
• The user reads the data from the current bank by using the USBFIFOnDATA register (see
• The user frees the bank and switches to the next bank (if any) by clearing FIFOCON.
If the endpoint uses several banks, the current one can be read while the following one is being
written by the host. Then, when the user clears FIFOCON, the following bank may already be
ready and RXOUTI is set immediately.
RXOUTE is one.
read, rather than polling RWALL.
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page
expected data frame is read or the bank is empty (in which case RWALL is cleared and BYCT
reaches zero).
HW
ACK
ACK
HW
SW
read data from CPU
SW
BANK 0
OUT
NAK
read data from CPU
BANK 0
(bank 1)
DATA
SW
OUT
ACK
(bank 0)
DATA
HW
SW
HW
ACK
483), until all the
AT32UC3B
read data from CPU
read data from CPU
SW
SW
BANK 1
BANK 0
390