AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 343

IC MCU AVR32 512K FLASH 64QFN

AT32UC3B0512-Z2UR

Manufacturer Part Number
AT32UC3B0512-Z2UR
Description
IC MCU AVR32 512K FLASH 64QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3B0512-Z2UR

Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
96K x 8
Program Memory Size
512KB (512K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0512-Z2UR
Manufacturer:
ATMEL
Quantity:
2 010
21.7.2
Name:
Access Type:
Offset:
Reset Value:
This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register(if exists).
32059J–12/2010
ONEBIT: Start Frame Delimiter Selector
MODSYNC: Manchester Synchronization Mode
MAN: Manchester Encoder/Decoder Enable
FILTER: Infrared Receive Line Filter
MAX_ITERATION
VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
DSNACK: Disable Successive NACK
INACK: Inhibit Non Acknowledge
OVER: Oversampling Mode
ONEBIT
31
23
15
7
0: Start Frame delimiter is COMMAND or DATA SYNC.
1: Start Frame delimiter is One Bit.
0:The Manchester Start bit is a 0 to 1 transition
1: The Manchester Start bit is a 1 to 0 transition.
0: Manchester Encoder/Decoder are disabled.
1: Manchester Encoder/Decoder are enabled.
0: The USART does not filter the receive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
Defines the maximum number of iterations in mode ISO7816, protocol T= 0.
0: User defined configuration of command or data sync field depending on SYNC value.
1: The sync field is updated when a character is written into THR register.
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a
0: The NACK is generated.
1: The NACK is not generated.
0: 16x Oversampling.
1: 8x Oversampling.
NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is
asserted.
Mode Register
CHMODE
CHRL
VAR_SYNC
MODSYNC
30
22
14
MR
Read-write
0x4
-
6
DSNACK
MAN
29
21
13
5
NBSTOP
USCLKS
FILTER
INACK
28
20
12
4
OVER
27
19
11
3
CLKO
PAR
26
18
10
2
MODE
MAX_ITERATION
MODE9
25
17
9
1
AT32UC3B
SYNC/CPHA
MSBF/CPOL
24
16
8
0
343

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