AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 158

IC MCU AVR32 512K FLASH 64QFN

AT32UC3B0512-Z2UR

Manufacturer Part Number
AT32UC3B0512-Z2UR
Description
IC MCU AVR32 512K FLASH 64QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3B0512-Z2UR

Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
96K x 8
Program Memory Size
512KB (512K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0512-Z2UR
Manufacturer:
ATMEL
Quantity:
2 010
16.6
16.6.1
Table 16-1.
16.6.2
Table 16-2.
Note:
32059J–12/2010
0x00C
0x01C
0x02C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
0x028
(0x000 - 0x03F)+m*0x040
User Interface
1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Offset
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
Address Range
0x000 - 0x03F
0x040 - 0x07F
Memory Map Overview
Channel Memory Map
PDCA Register Memory Map
PDCA Channel Configuration Registers
...
The channels are mapped as shown in
isters, shown in
Note:
Memory Address Reload Register
Transfer Counter Reload Register
Memory Address Register
Peripheral Select Register
Transfer Counter Register
Interrupt Disable Register
Interrupt Enable Register
Interrupt Status Register
Interrupt Mask Register
1. The reset values are device specific. Please refer to the Module Configuration section at the
Control Register
Status Register
Mode Register
end of this chapter.
Register
Table
16-2, where n is the channel number.
DMA channel m configuration registers
DMA channel 0 configuration registers
DMA channel 1 configuration registers
Table
Register Name
MARR
16-1. Each channel has a set of configuration reg-
TCRR
MAR
PSR
TCR
IMR
IER
IDR
ISR
MR
Contents
CR
SR
...
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Access
AT32UC3B
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
-
(1)
158

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