AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 376

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.7.1.5
22.7.1.6
32059J–12/2010
Speed control
DPRAM management
•USB Suspend mode
•Device mode
•Host mode
• The Host Wake-up Interrupt (HWUPI)
In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register
(UDINT.SUSP)indicates that the USB line is in the suspend mode. In this case, the USB Data
UTMI transceiver is automatically set in suspend mode to reduce the consumption.
When the USBB interface is in device mode, the speed selection (full-/low-speed) depends on
which of D+ and D- is pulled up. The LS bit allows to connect an internal pull-up resistor either
on D+ (full-speed mode) or on D- (low-speed mode). The LS bit shall be written before attaching
the device, what can be done by clearing the DETACH bit in UDCON.
Figure 22-7. Speed Selection in Device Mode
When the USB interface is in host mode, internal pull-down resistors are connected on both D+
and D- and the interface detects the speed of the connected device, which is reflected by the
Speed Status (SPEED) field in USBSTA.
Pipes and endpoints can only be allocated in ascending order (from the pipe/endpoint 0 to the
last pipe/endpoint to be allocated). The user shall therefore configure them in the same order.
The allocation of a pipe/endpoint n starts when the Endpoint Memory Allocate bit in the Endpoint
n Configuration register (UECFGn.ALLOC) is written to one. Then, the hardware allocates a
memory area in the DPRAM and inserts it between the n-1 and n+1 pipes/endpoints. The n+1
pipe/endpoint memory window slides up and its data is lost. Note that the following pipe/end-
point memory windows (from n+2) do not slide.
Disabling a pipe, by writing a zero to the Pipe n Enable bit in the Pipe Enable/Reset register
(UPRST.PENn), or disabling an endpoint, by writing a zero to the Endpoint n Enable bit in the
Endpoint Enable/Reset register (UERST.EPENn), resets neither the UECFGn.ALLOC bit nor its
VBUS
D+
D-
UDCON.DETACH
UDCON.LS
AT32UC3B
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