AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 459

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.8.3.5
Register Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
•
•
•
•
•
32059J–12/2010
DMAnINTE: DMA Channel n Interrupt Enable
PnINTE: Pipe n Interrupt Enable
HWUPIE: Host Wake-Up Interrupt Enable
HSOFIE: Host Start of Frame Interrupt Enable
RXRSMIE: Upstream Resume Received Interrupt Enable
RSMEDIE: Downstream Resume Sent Interrupt Enable
RSTIE: USB Reset Sent Interrupt Enable
DDISCIE: Device Disconnection Interrupt Enable
DCONNIE: Device Connection Interrupt Enable
31
23
15
7
-
-
-
-
This bit is set when the DMAnINTES bit is written to one. This will enable the DMA Channel n Interrupt (DMAnINT).
This bit is cleared when the DMAnINTEC bit is written to one. This will disable the DMA Channel n Interrupt (DMAnINT).
This bit is set when the PnINTES bit is written to one. This will enable the Pipe n Interrupt (PnINT).
This bit is cleared when the PnINTEC bit is written to one. This will disable the Pipe n Interrupt (PnINT).
This bit is set when the HWUPIES bit is written to one. This will enable the Host Wake-up Interrupt (HWUPI).
This bit is cleared when the HWUPIEC bit is written to one. This will disable the Host Wake-up Interrupt (HWUPI).
This bit is set when the HSOFIES bit is written to one. This will enable the Host Start of Frame interrupt (HSOFI).
This bit is cleared when the HSOFIEC bit is written to one. This will disable the Host Start of Frame interrupt (HSOFI).
This bit is set when the RXRSMIES bit is written to one. This will enable the Upstream Resume Received interrupt (RXRSMI).
This bit is cleared when the RXRSMIEC bit is written to one. This will disable the Downstream Resume interrupt (RXRSMI).
This bit is set when the RSMEDIES bit is written to one. This will enable the Downstream Resume interrupt (RSMEDI).
This bit is cleared when the RSMEDIEC bit is written to one. This will disable the Downstream Resume interrupt (RSMEDI).
This bit is set when the RSTIES bit is written to one. This will enable the USB Reset Sent interrupt (RSTI).
This bit is cleared when the RSTIEC bit is written to one. This will disable the USB Reset Sent interrupt (RSTI).
This bit is set when the DDISCIES bit is written to one. This will enable the Device Disconnection interrupt (DDISCI).
This bit is cleared when the DDISCIEC bit is written to one. This will disable the Device Disconnection interrupt (DDISCI).
This bit is set when the DCONNIES bit is written to one. This will enable the Device Connection interrupt (DCONNI).
This bit is cleared when the DCONNIEC bit is written to one. This will disable the Device Connection interrupt (DCONNI).
Host Global Interrupt Enable Register
DMA6INTE
HWUPIE
P6INTE
30
22
14
6
-
UHINTE
Read-Only
0x0410
0x00000000
DMA5INTE
HSOFIE
P5INTE
29
21
13
5
-
DMA4INTE
RXRSMIE
P4INTE
28
20
12
4
-
DMA3INTE
RSMEDIE
P3INTE
27
19
11
3
-
DMA2INTE
P2INTE
RSTIE
26
18
10
2
-
DMA1INTE
DDISCIE
P1INTE
25
17
9
1
-
AT32UC3B
DCONNIE
P0INTE
24
16
8
0
-
-
459