AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 43
AT32UC3B0512-Z2UR
Manufacturer Part Number
AT32UC3B0512-Z2UR
Description
IC MCU AVR32 512K FLASH 64QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B0512-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
96K x 8
Program Memory Size
512KB (512K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
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Part Number:
AT32UC3B0512-Z2UR
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ATMEL
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Table 9-1.
9.5.7.3
9.5.7.4
9.5.8
32059J–12/2010
Index
3
4
5
Generic clocks
Sleep Mode
Stop
DeepStop
Static
Precautions when entering sleep mode
Wake Up
Sleep modes
The power level of the internal voltage regulator is also adjusted according to the sleep mode to
reduce the internal regulator power consumption.
Modules communicating with external circuits should normally be disabled before entering a
sleep mode that will stop the module operation. This prevents erratic behavior when entering or
exiting sleep mode. Please refer to the relevant module documentation for recommended
actions.
Communication between the synchronous clock domains is disturbed when entering and exiting
sleep modes. This means that bus transactions are not allowed between clock domains affected
by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus
transaction.
The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are com-
plete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is
necessary.
When entering a sleep mode (except Idle mode), all HSB masters must be stopped before
entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete,
the CPU should perform a read operation from any register on the PB bus before executing the
sleep instruction. This will stall the CPU while waiting for any pending PB operations to
complete.
The USB can be used to wake up the part from sleep modes through register AWEN of the
Power Manager.
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The Power Manager contains an implementation
defined number of generic clocks that can provide a wide range of accurate clock frequencies.
Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source
can optionally be divided by any even integer up to 512. Each clock can be independently
enabled and disabled, and is also automatically disabled along with peripheral clocks by the
Sleep Controller.
CPU
Stop
Stop
Stop
HSB
Stop
Stop
Stop
PBA,B
GCLK
Stop
Stop
Stop
Osc0,1
PLL0,1,
SYSTIMER
Stop
Stop
Stop
Osc32
Run
Run
Stop
RCOsc
Run
Run
Stop
BOD &
Bandgap
On
Off
Off
AT32UC3B
Voltage
Regulator
Low power
Low power
Low power
43
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