AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 452

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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32059J–12/2010
LDNXTCHDES
BUFFCLOSEINEN: Buffer Close Input Enable
LDNXTCHDESCEN: Load Next Channel Descriptor Enable
CHEN: Channel Enable
CEN
For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB
For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero.
Writing a zero to this bit to disable this feature.
1: the channel controller loads the next descriptor after the end of the current transfer, i.e. when the UDDMAnSTATUS.CHEN bit
0: no channel register is loaded after the end of the channel transfer.
If the CHEN bit is written to zero, the next descriptor is immediately loaded upon transfer request (endpoint is free for IN
Writing this bit to zero will disabled the DMA channel and no transfer will occur upon request. If the LDNXTCHDESCEN bit is
Writing this bit to one will set the UDDMAnSTATUS.CHEN bit and enable DMA channel data transfer. Then any pending request
This bit is cleared when the channel source bus is disabled at end of buffer. If the LDNXTCHDESCEN bit has been cleared by
If a channel request is currently serviced when this bit is zero, the DMA FIFO buffer is drained until it is empty, then the
If the LDNXTCHDESCEN bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer
0
0
1
1
OUT data transfer (received short packet).
is reset.
endpoint, or endpoint is full for OUT endpoint).
written to zero, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both
UDDMAnSTATUS.CHEN and CHACTIVE bits are zero.
will start the transfer. This may be used to start or resume any requested transfer.
descriptor loading, the user will have to write to one the corresponding CHEN bit to start the described transfer, if needed.
UDDMAnSTATUS.CHEN bit is cleared.
occurs) and the next descriptor is immediately loaded.
CHEN
Table 22-6.
0
1
0
1
Current Bank
stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
DMA Channel Control Command Summary
AT32UC3B
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