AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 312

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

32059J–12/2010
the TXSYNH in the THR register. The USART character format is modified and includes sync
information.
The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the
middle of the second bit time. Two distinct sync patterns are used: the command sync and the
data sync. The command sync has a logic one level for one and a half bit times, then a transition
to logic zero for the second one and a half bit times. If the MODSYNC field in the MR register is
set to 1, the next character is a command. If it is set to 0, the next character is a data. When
direct memory access is used, the MODSYNC field can be immediately updated with a modified
character located in memory. To enable this mode, VAR_SYNC field in MR register must be set
to 1. In this case, the MODSYNC field in MR is bypassed and the sync configuration is held in
Figure 21-9. Start Frame Delimiter
Drift Compensation
Drift compensation is available only in 16X oversampling mode. An hardware recovery system
allows a larger clock drift. To enable the hardware system, the bit in the MAN register must be
set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as nor-
mal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles
before the expected edge, then the current period is shortened by one clock cycle. If the RXD
event is between 2 and 3 clock cycles after the expected edge, then the current period is length-
ened by one clock cycle. These intervals are considered to be drift and so corrective actions are
automatically taken.
Manchester
Manchester
Manchester
encoded
encoded
encoded
data
data
data
Preamble Length
Txd
Txd
Txd
is set to 0
SFD
SFD
SFD
DATA
One bit start frame delimiter
start frame delimiter
start frame delimiter
DATA
DATA
Command Sync
Data Sync
AT32UC3B
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