AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 64

• Manufacturer Part Number: AT91SAM9R64-CU-999
• Description: IC MCU ARM9 64K SRAM 144LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.6.2.2
12.7
12.7.1
64
Write-though Operation
Write-back Operation
Tightly-Coupled Memory Interface
AT91SAM9R64/RL64 Preliminary
TCM Description
Write Buffer
The DCache contains an eight data word entry, single address entry write-back buffer used to
hold write-back data for cache line eviction or cleaning of dirty cache lines.
The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and
Write Buffer operations are closely connected as their configuration is set in each section by the
page descriptor in the MMU translation table.
The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buf-
fer. The write buffer is used for all writes to a bufferable region, write-through region and write-
back region. It also allows to avoid stalling the processor when writes to external memory are
performed. When a store occurs, data is written to the write buffer at core speed (high speed).
The write buffer then completes the store to external memory at bus speed (typically slower than
the core speed). During this time, the ARM9EJ-S processor can preform other tasks.
DCache and Write Buffer support write-back and write-through memory regions, controlled by C
and B bits in each section and page descriptor within the MMU translation tables.
When a cache write hit occurs, the DCache line is updated. The updated data is then written to
the write buffer which transfers it to external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in
the write buffer which transfers it to external memory.
When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its
contents are not up-to-date with those in the external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in
the write buffer which transfers it to external memory.
The ARM926EJ-S processor features a Tightly-Coupled Memory (TCM) interface, which
enables separate instruction and data TCMs (ITCM and DTCM) to be directly reached by the
processor. TCMs are used to store real-time and performance critical code, they also provide a
DMA support mechanism. Unlike AHB accesses to external memories, accesses to TCMs are
fast and deterministic and do not incur bus penalties.
The user has the possibility to independently configure each TCM size with values within the fol-
lowing ranges, [0KB, 32 KB] for ITCM size and [0KB, 32 KB] for DTCM size.
TCMs can be configured by two means: HMATRIX TCM register and TCM region register (regis-
ter 9) in CP15 and both steps should be performed. HMATRIX TCM register sets TCM size
whereas TCM region register (register 9) in CP15 maps TCMs and enables them.
The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable
code to be loaded into the ITCM, for SWI and emulated instruction handlers, and for accesses to
PC-relative literal pools.
6289C–ATARM–28-May-09