AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 717
![IC MCU ARM9 64K SRAM 144LFBGA](/photos/12/13/121356/144-lfbga_sml.jpg)
AT91SAM9R64-CU-999
Manufacturer Part Number
AT91SAM9R64-CU-999
Description
IC MCU ARM9 64K SRAM 144LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9R64-CU.pdf
(903 pages)
Specifications of AT91SAM9R64-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
SPI, TWI, UART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
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Price
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40.6.4
40.6.4.1
40.6.4.2
6289C–ATARM–28-May-09
Wake-up Triggered by the AC’97 Controller
Wake-up Triggered by the AC97 Codec
Power Management
Powering Down the AC-Link
Waking up the AC-link
Codec to the AC’97 Controller in slot 1/SLOTREQ in every audio input frame. Each time the
AC‘97 controller sees one or more of the newly defined slot request flags set active (low) in a
given audio input frame, it must pass along the next PCM sample for the corresponding slot(s) in
the AC-link output frame that immediately follows.
The variable Sample Rate mode is enabled by performing the following steps:
Slot 1 of the input frame is automatically interpreted as SLOTREQ signaling bits. The AC’97
Controller will automatically fill the active slots according to both SLOTREQ and AC97C_OCA
register in the next transmitted frame.
The AC97 Codecs can be placed in low power mode. The application can bring AC97 Codec to
a power down state by performing sequential writes to AC97 Codec powerdown register. Both
the bit clock (clock delivered by AC97 Codec, AC97CK) and the input line (AC97RX) are held at
a logic low voltage level. This puts AC97 Codec in power down state while all its registers are
still holding current values. Without the bit clock, the AC-link is completely in a power down
state.
The AC’97 Controller should not attempt to play or capture audio data until it has awakened
AC97 Codec.
To set the AC’97 Codec in low power mode, the PR4 bit in the AC’97 Codec powerdown register
(Codec address 0x26) must be set to 1. Then the primary Codec drives both AC97CK and
AC97RX to a low logic voltage level.
The following operations must be done to put AC97 Codec in low power mode:
At this point AC97 Codec is in low power mode.
There are two methods to bring the AC-link out of low power mode. Regardless of the method, it
is always the AC97 Controller that performs the wake-up.
The AC’97 Controller can wake up the AC97 Codec by issuing either a cold or a warm reset.
The AC’97 Controller can also wake up the AC97 Codec by asserting AC97FS signal, however
this action should not be performed for a minimum period of four audio frames following the
frame in which the powerdown was issued.
• Setting the VRA bit in the AC’97 Controller Mode Register (AC97C_MR).
• Enable Variable Rate mode in the AC‘97 Codec by performing a transfer on the Codec
• Disable Channel A clearing CEN in the AC97C_CAMR register.
• Disable Channel B clearing CEN field in the AC97C_CBMR register.
• Write 0x2680 value in the AC97C_COTHR register.
• Poll the TXEMPTY flag in AC97C_CxSR registers for the 2 channels.
channel.
AT91SAM9R64/RL64 Preliminary
717
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