AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 664

• Manufacturer Part Number: AT91SAM9R64-CU-999
• Description: IC MCU ARM9 64K SRAM 144LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 39-4. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1
Figure 39-5. TFT Panel Timing (Line Expanded View), CLKMOD=1
664
LCDHSYNC
LCDVSYNC
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDOTCK
LCDVSYNC
LCDHSYNC
LCDDEN
LCDDOTCK
LCDDEN
LCDDEN
AT91SAM9R64/RL64 Preliminary
LCDD
LCDD
LCDD
VHDLY+1
VHDLY+1
Vertical Back Porch = VBP Lines
VHDLY+1
--------------------------- -
f
LCDVSYNC
Usually the LCD_FRM rate is about 70 Hz to 75 Hz. It is given by the following equation:
where:
In STN Mode:
1
• HOZVAL determines de number of LCDDOTCK cycles per line
• LINEVAL determines the number of LCDHSYNC cycles per frame, according to the
HPW+1
HPW+1
expressions shown below:
(VPW+1) Lines
=
⎛
⎝
VHDLY
-------------------------------------------------------------------------------------------------------------------- -
HBP+1
HBP+1
HOZVAL
+
1 PCLK
HPW
1 PCLK
=
Horizontal_display_size
-------------------------------------------------------------- - 1
+
Line Period
Line Period
f
HBP
LCDDOTCK
Number_data_lines
Frame Period
1/2 PCLK 1/2 PCLK
+
1/2 PCLK 1/2 PCLK
HOZVAL
+
HOZVAL+1
HFP
HOZVAL+1
–
+
5
⎞ VBP
⎠
(
+
LINEVAL
Vertical Fron t Porch = VFP Lines
+
6289C–ATARM–28-May-09
VFP
HFP+1
HFP+1
+
1
)