AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 838

• Manufacturer Part Number: AT91SAM9R64-CU-999
• Description: IC MCU ARM9 64K SRAM 144LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

43.10 Touch Screen ADC Controller (TSADCC) User Interface
Table 43-2.
6289C–ATARM–28-May-09
0x48 - 0xFC
Offset
0x0C
0x1C
0x2C
0x3C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
Register Mapping
Register
Control Register
Mode Register
Trigger Register
Touch Screen Register
Channel Enable Register
Channel Disable Register
Channel Status Register
Status Register
Last Converted Data Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Channel Data Register 0
Channel Data Register 1
Channel Data Register 2
Channel Data Register 3
Channel Data Register 4
Channel Data Register 5
Reserved
AT91SAM9R64/RL64 Preliminary
TSADCC_TRGR
TSADCC_CHER
TSADCC_CHDR
TSADCC_CHSR
TSADCC_LCDR
TSADCC_CDR0
TSADCC_CDR1
TSADCC_CDR2
TSADCC_CDR3
TSADCC_CDR4
TSADCC_CDR5
TSADCC_TSR
TSADCC_IMR
TSADCC_IER
TSADCC_IDR
TSADCC_MR
TSADCC_CR
TSADCC_SR
Name
–
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Access
–
0x000C_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
–
–
–
–
–
–
838