AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 832

• Manufacturer Part Number: AT91SAM9R64-CU-999
• Description: IC MCU ARM9 64K SRAM 144LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 43-4. Touch Screen Pen Detect
43.7
832
Conversion Results
AT91SAM9R64/RL64 Preliminary
X
Y
X
Y
M
M
P
P
Screen panel when the system is running at high speed. The debouncer length can be selected
by programming the field PENDBC in
The Touch Screen Pen Detect can be used to generate a TSADCC interrupt to wake up the sys-
tem or it can be programmed to trig a conversion, so that a position can be measured as soon as
a contact is detected if the TSADCC is programmed for an operating mode involving the Touch
Screen.
The Pen Detect generates two types of status, reported in the
Both bits are automatically cleared as soon as the Status Register TSADCC_SR is read, and
can generate an interrupt by writing accordingly the
When a conversion is completed, the resulting 8-bit or 10-bit digital value is right-aligned and
stored in the
“TSADCC Last Converted Data
The channel EOC bit and the bit DRDY in the
PDC channel is enabled, DRDY rising triggers a data transfer. In any case, either EOC and
DRDY can trigger an interrupt.
Reading one of the
sponding EOC bit.
Reading
sponding to the last converted channel.
• the bit PENCNT is set as soon as a current flows for a time over the debouncing time as
• the bit NOCNT is set as soon as no current flows for a time over the debouncing time as
defined by PENDBC and remains set until TSADCC_SR is read.
defined by PENDBC and remains set until TSADCC_SR is read.
“TSADCC Last Converted Data Register”
VDDANA
VDDANA
GND
GND
“TSADCC Channel Data Register x (x = 0..5)”
“TSADCC Channel Data Register x (x = 0..5)”
GND
Register”.
“TSADCC Mode
To the ADC
“TSADCC Status Register”
clears the DRDY bit and the EOC bit corre-
“TSADCC Interrupt Enable
Debouncer
PENDBC
Register”.
of the current channel and in the
“TSADCC Status
Pen Interrupt
registers clears the corre-
6289C–ATARM–28-May-09
are both set. If the
Register”.
Register”: