ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 110

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
13.3.3 - Block Diagram
Figure 53 : XTIMER Block Diagram
13.3.3.1 - Clocks
The XTCVR register clock is the prescaler output.
The prescaler allows to divide the basic register
frequency in order to offer a wide range of count-
ing period, from 2**2 to 2**33 cycles (note that 1
cycle = 1 XCLK periods).
13.3.3.2 - Registers
The XTCVR register input is linked to several
sources:
– XTSVR register (start value) for reload when the
– Incrementer output when the ’up’ mode is selected,
– Decrementer output when the ’down’ mode is
– The selection between the sources is made
When starting the timer, by setting TEN bit of TCR
to ’1’, XTCVR will be loaded with XTSVR value on
the first rising edge of the counting clock. That’s to
say that for counting from 0000h to 0009h for
110/186
period is finished, or for load when the timer is
starting.
selected.
through the XTCR control register.
Timer output
(XADCINJ)
diff
XTCR
ctl
XTEVR
ctl
ctl
=
Prescaling
XCLK
DATA
example, 10 counting clock rising edges are
required.
The XTCVR register output is continuously com-
pared to the XTEVR register to detect the end of
the counting period. When the registers are equal,
several actions are made depending on the XTCR
control register content :
– The output XADCINJ is conditionally generated,
– XTCVR is loaded with XTSVR or stops or contin-
XTEVR, XTSVR and all TCR bits except TEN
must not be modified while the timer is counting,
ie while TEN bit of TCR = ’1’. The timer behaviour
is not guaranteed if this rule is not respected. It
implies that the timer can be configured only when
stopped (TEN = ’0’). When programming the
timer, XTEVR, XTSVR and XTCR bits except TEN
can be modified, with TEN = ’0’; then the timer is
started by modifying only TEN bit of TCR. To stop
the timer, only TEN bit should be modified, from ’1’
to ’0’.
ues to count (see Table 22).
+ 1
ctl
XTCVR
- 1
XTSVR