ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 4

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
12.10 -
12.10.1 -
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12.12 -
12.12.1 -
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13.1 -
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13.3.1 -
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13.3.2.1 -
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13.3.2.4 -
13.3.2.5 -
13.3.3 -
13.3.3.1 -
13.3.3.2 -
13.3.3.3 -
14 -
14.1 -
14.1.1 -
14.1.2 -
14.2 -
15 -
15.1 -
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PORT 8 .......................................................................................................................
Alternate Functions of Port 8 ......................................................................................
XPORT 9 ....................................................................................................................
XPORT 10 ..................................................................................................................
Alternate Functions of XPort 10 ..................................................................................
New Disturb Protection on Analog Inputs ...................................................................
A/D CONVERTER ......................................................................................................
A/D CONVERTER MODULE ......................................................................................
MULTIPLEXAGE OF TWO BLOCKS OF 16 ANALOG INPUTS ................................
XTIMER PERIPHERAL (TRIGGER FOR ADC CHANNEL INJECTION) ...................
Main Features .............................................................................................................
Register Description ...................................................................................................
TCR : Timer Control Register ......................................................................................
XTSVR :Timer Start Value Register ............................................................................
XTEVR : Timer End Value Register ............................................................................
XTCVR : Timer Current Value Register.......................................................................
Registers Mapping.......................................................................................................
Block Diagram ...........................................................................................................
Clocks ..........................................................................................................................
Registers .....................................................................................................................
Timer output (XADCINJ)..............................................................................................
SERIAL CHANNELS .................................................................................................
ASYNCHRONOUS / SYNCHRONOUS SERIAL INTERFACE (ASCO) ....................
ASCO in Asynchronous Mode ....................................................................................
ASCO in Synchronous Mode ......................................................................................
HIGH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC) .....................................
CAN MODULES .........................................................................................................
MEMORY MAPPING ..................................................................................................
CAN1 .................................................................................................................. ........
CAN2 .................................................................................................................. ........
CAN BUS CONFIGURATIONS ..................................................................................
REGISTER AND MESSAGE OBJECT ORGANIZATION ..........................................
CAN INTERRUPT HANDLING .................................................................................
THE MESSAGE OBJECT ..........................................................................................
ARBITRATION REGISTERS ......................................................................................
WATCHDOG TIMER ..................................................................................................
SYSTEM RESET ........................................................................................................
ASYNCHRONOUS RESET (LONG HARDWARE RESET) .......................................
SYNCHRONOUS RESET (WARM RESET) ..............................................................
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130
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