ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 93

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Port 5 pins have a special port structure (see Figure 43), first because it is an input only port, and second
because the analog input channels are directly connected to the pins rather than to the input latches.
Figure 43 : Block Diagram of a Port 5 Pin
12.7.1 - Port 5 Schmitt Trigger Analog Inputs
A Schmitt trigger protection can be activated on each pin of Port 5 by setting the dedicated bit of register
P5DIDIS.
P5DIDIS (FFA4h / D2h)
12.8 - Port 6
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corre-
sponding direction register DP6. Each port line can be switched into push/pull or open drain mode via the
open drain control register ODP6.
P6 (FFCCh / E6h)
DP6 (FFCEh / E7h)
DIS.15
P5DIDIS.y
P6.y
P5DI
RW
15
15
15
-
-
Bit
DIS.14
Bit
P5DI
RW
14
14
14
-
-
DIS.13
P5DI
RW
13
13
13
-
-
Port 5 Digital Disablel register bit y
P5DIDIS.y = 0: Port line P5.y digital input is enabled (Schmitt trigger enabled)
P5DIDIS.y = 1: Port line P5.y digital input is disabled (Schmitt trigger disabled, necessary for input
leakage current reduction)
Port data register P6 bit y
DIS.12
P5DI
RW
12
12
12
-
-
DIS.11
P5DI
RW
11
11
11
-
-
to Sample + Hold
DIS.10
P5DI
RW
10
10
10
Circuit
Read
Buffer
-
-
Read Port P5.y
DIS.9
P5DI
RW
9
9
9
-
-
DIS.8
P5DI
RW
8
8
8
-
-
Channel
SFR
SFR
SFR
Select
DP6.7 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6.0
DIS.7
CPU Clock
P5DI
P6.7
RW
RW
RW
7
7
7
Latch
Input
Function
Function
DIS.6
P5DI
P6.6
RW
RW
RW
6
6
6
Analog
Switch
DIS.5
P5DI
P6.5
RW
RW
RW
5
5
5
DIS.4
P5DI
P6.4
RW
RW
RW
4
4
4
P5.y/ANy
DIS.3
P5DI
P6.3
RW
RW
RW
3
3
3
Reset Value: - - 00h
Reset Value: - - 00h
Reset Value: 0000h
DIS.2
P5DI
P6.2
RW
RW
RW
2
2
2
y = 15...0
DIS.1
P5DI
ST10F280
P6.1
RW
RW
RW
1
1
1
93/186
DIS.0
P5DI
P6.0
RW
RW
RW
0
0
0