ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 120

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Control / Status Register (EF00h/EE00h)
Table 27 : CAN Control/Status Register
120/186
BOFF EWRN
15
R
CCE
LEC
INIT
TST
SIE
EIE
Bit
IE
14
R
Initialization
1:
0:
Interrupt Enable Does not affect status updates.
1:
0:
Status Change Interrupt Enable
1:
0:
Error Interrupt Enable
1:
0:
Configuration Change Enable
1:
0:
Test Mode (Bit 7)
Make sure that bit 7 is cleared when writing to the Control Register. Writing a 1 during normal operation
may lead erroneous device behaviour.
Last Error Code
This field holds a code which indicates the type of the last error occurred on the CAN bus. If a message has
been transferred (reception or transmission) without error, this field will be cleared. Code “7” is unused and
may be written by the CPU to check for updates.
0:
1:
2:
3:
4:
5:
6:
13
-
Software initialization of the CAN controller. While init is set, all message transfers are stopped.
Setting init does not change the configuration registers and does not stop transmission or
reception of a message in progress. The INIT bit is also set by hardware, following a busoff
condition; the CPU then needs to reset INIT to start the bus recovery sequence.
Disable software initialization of the CAN controller; on INI completion, the CAN waits for 11
consecutive recessive bit before taking part in bus activities.
Global interrupt enable from CAN module.
Global interrupt disable from CAN module.
Enables interrupt generation when a message transfer (reception or transmision is successfully
completed) or CAN bus error is detected and registered in LEC is the status partition.
Disable status change interrupt.
Enables interrupt generation on a change of bit BOFF or EWARN in the status partition.
Disable error interrupt.
Allows CPU access to the bit timing register
Disables CPU access to the bit timing register
No Error
Stuff Error: More than 5 equal bit in a sequence have occurred in a part of a received message
where this is not allowed.
Form Error: A fixed format part of a received frame has the wrong format.
AckError: The message this CAN controller transmitted was not acknowledged by another node
Bit1Error: During the transmission of a message (with the exception of the arbitration field), the
device wanted to send a recessive level (“1”), but the monitored bus value was dominant
Bit0Error: During the transmission of a message (or acknowledge bit, active error flag, or overload
flag), the device wanted to send a dominant level (“0”), but the monitored bus value was recessive .
During busoff recovery this status is set each time a sequence of 11 recessive bit has been
monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence
(indicating the bus is not stuck at dominant or continuously disturbed).
CRCError: The CRC check sum was incorrect in the message received.
RXOK TXOK
RW
12
RW
11
10
LEC
RW
9
Function (Control Bit)
8
XReg
TST
RW
7
CCE
RW
6
R
5
0
R
4
0
RW
EIE
3
Reset Value: XX01h
SIE
RW
2
RW
IE
1
INIT
RW
0