ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 157

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ST10F280

Manufacturer Part Number
ST10F280
Description
MCU 16BIT 512K FLASH MAC 208-PBG
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F280

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, SSC
Peripherals
POR, PWM, WDT
Number Of I /o
143
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
18K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 32x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
208-PBGA
Processor Series
ST10F28x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Figure 74 : Supply / Idle Current as a Function of Operating Frequency
5. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for
CS output and if their open drain function is not enabled.
6. The maximum current may be drawn while the respective signal line remains inactive.
7. The minimum current must be drawn in order to drive the respective signal line active.
8. The power supply current is a function of the operating frequency. This dependency is illustrated in the Figure 74. These
parameters are tested at V
configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during
reset. After reset, PORT 0 is driven with the value ‘00CCh’ that produces infinite execution of NOP instruction with 15 wait-state, R/
W delay, memory tristate wait state, normal ALE. Peripherals are not activated.
9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 74. These
parameters are tested at V
10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0 V to 0.1V or at
V
DD
300
– 0.1V to V
10
DD
, V
REF
= 0V, all outputs (including pins configured as outputs) disconnected.
DD
DD
max and 40MHz CPU clock with all outputs disconnected and all inputs at V
10
max and 40MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is
20
30
I
I
I
I
CCmax
CCtyp
IDmax
IDtyp
40
f
CPU
IL
162mA
or V
[MHz]
IH
70mA
.
ST10F280
157/186

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