ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 181

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing
20.4.14.1 Master Mode
V
Note: 1. Timing guaranteed by design.
The formula for SSC Clock Cycle time is : t
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.
Figure 91 : SSC Master Timing
Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn
t
t
CC
t
t
t
t
t
t
t
t
t
307p
308p
300
301
302
303
304
305
306
307
308
Symbol
= 5V ±10%, V
in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
SCLK
MTSR
MRST
CC SSC clock cycle time
CC SSC clock high time
CC SSC clock low time
CC SSC clock rise time
CC SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge
SR Read data setup time before
SR Read data hold time after latch
SR Read data setup time before
SR Read data hold time after latch
latch edge, phase error
detection on (SSCPEN = 1)
edge, phase error detection on
(SSCPEN = 1)
latch edge, phase error
detection off (SSCPEN = 0)
edge, phase error detection off
(SSCPEN = 0)
1)
SS
= 0V, CPU clock = 40MHz, T
Parameter
t
305
1st.In Bit
t
307
t
300
1st Out Bit
t
308
t
t
301
305
t
304
1
Maximum Baud rate = 10M Baud
300
2nd Out Bit
Minimum
t
2nd.In Bit
302
= 4 TCL * (<SSCBR> + 1)
37.5
100
(<SSCBR> = 0001h)
40
40
50
25
-2
–
–
–
0
A
= -40 to +125°C, C
t
303
t
306
Maximum
2)
100
10
10
15
–
–
–
–
–
–
–
t
L
305
= 50pF
t
Last.In Bit
307
2 TCL + 12.5
(<SSCBR>=0001h-FFFFh) Unit
t
t
Minimum
300
300
Last Out Bit
8 TCL
4 TCL
2 TCL
Variable Baud rate
t
308
/2 - 10
/2 - 10
-2
–
–
–
0
262144 TCL
Maximum
10
10
15
–
–
–
–
–
–
–
ST10F280
181/186
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns