ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 58

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Figure 15 : Block Diagram of GPT1
10.2 - GPT2
The GPT2 module provides precise event control
and time measurement. It includes two timers (T5,
T6) and a capture/reload register (CAPREL). Both
timers can be clocked with an input clock which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction
programmable by software or may additionally be
altered dynamically by an external signal on a port
pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of
timer T6 which changes its state on each timer
overflow/underflow.
The state of this latch may be used to clock timer
T5, or it may be output on a port pin (T6OUT). The
overflow / underflow of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
Table 12 : GPT2 Timer Input Frequencies, Resolution and Period
58/186
Pre-scaler factor
Input Freq
Resolution
Period maximum
f
CPU
= 40MHz
CPU Clock
CPU Clock
CPU Clock
T3EUD
T2EUD
T4EUD
T2IN
T3IN
(up/down)
T4IN
2
2
2
n
n
n
6.55ms
10MHz
100ns
n=3...10
n=3...10
n=3...10
000b
4
for
13.1ms
200ns
5MHz
001b
each
8
T2
Mode
Control
T3
Mode
Control
T4
Mode
Control
timer
2.5MHz
26.2ms
400ns
010b
16
Timer Input Selection T5I / T6I
is
Reload
Capture
Capture
Reload
1.25MHz
52.4ms
0.8µs
011b
32
and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of
timer T5 based on an external signal transition on
the corresponding port pin (CAPIN), and timer T5
may optionally be cleared after the capture
procedure. This allows absolute time differences
to be measured or pulse multiplication to be
performed without software overhead.
The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT1 timer
T3
advantageous when T3 operates in Incremental
Interface Mode.
Table 12 lists the timer input frequencies,
resolution and periods for each pre-scaler option
at 40MHz CPU clock. This also applies to the
Gated Timer Mode of T6 and to the auxiliary timer
T5 in Timer and Gated Timer Mode.
U/D
GPT1 Timer T3
GPT1 Timer T4
GPT1 Timer T2
inputs
104.8ms
625kHz
1.6µs
100b
64
U/D
U/D
T3IN
312.5kHz
209.7ms
3.2µs
101b
128
and/or
T3OTL
156.25kHz
419.4ms
6.4µs
110b
T3EUD.
256
Request
Interrupt
Interrupt
Request
Request
Interrupt
T3OUT
78.125kHz
838.9ms
This
12.8µs
111b
512
is