ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 35

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

When the ST10F280 has entered BSL mode, the following configuration is automatically set (values that
deviate from the normal reset values, are marked ):
In this case, the watchdog timer is disabled, so the
bootstrap loading sequence is not time limited.
Pin TXD0 is configured as output, so the
ST10F280 can return the identification Byte.
Even if the internal Flash is enabled, no code can
be executed out of it.
The hardware that activates the BSL during reset
may be a simple pull-down resistor on P0L.4 for
systems that use this feature upon every
hardware reset.
A switchable solution (via jumper or an external
signal)
only temporarily use the bootstrap loader (see
Figure 6).
After
ASC0 receiver is enabled and is ready to
receive the initial 32 Bytes from the host. A half
duplex connection is therefore sufficient to feed
the BSL.
Figure 6 : Hardware Provisions to Activate the BSL
Watchdog Timer:
Context Pointer CP:
Stack Pointer SP:
Register S0CON:
Register S0BG:
sending
can
POL.4
be
the
used
identification
Disabled
FA00h
FA40h
8011h
Acc. to ‘00’ Byte
for
R
8k
Circuit 1
systems
POL.4
Byte
that
the
Register SYSCON:
Register STKUN:
Register STKOV:
Register BUSCON0:
P3.10 / TXD0:
DP3.10:
5.6.2 - Memory Configuration After Reset
The configuration (and the accessibility) of the
ST10F280’s
Bootstrap-Loader mode differs from the standard
case. Pin EA is not evaluated when BSL mode is
selected, and accesses to the internal Flash area
are partly redirected, while the ST10F280 is in
BSL mode (see Figure 7). All code fetches are
made from the special Boot-ROM, while data
accesses read from the internal user Flash. Data
accesses
ROMless devices.
The code in the Boot-ROM is not an invariant
feature of the ST10F280. User software should
not try to execute code from the internal Flash
area while the BSL mode is still active, as these
fetches will be redirected to the Boot-ROM. The
Boot-ROM will also “move” to segment 1, when
the internal Flash area is mapped to segment 1
(see Figure 7).
POL.4
will
memory
return
0E00h
FA40h
FA0Ch 0<->C
acc. to startup configuration
‘1’
‘1’
External
Signal
areas
undefined
BSL
R
8k
Circuit 2
Normal Boot
POL.4
after
ST10F280
values
reset
35/186
on
in