ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 124

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Lower Global Mask Long (EF0Ah/EE0Ah)
Upper Mask of Last Message (EF0Ch/EE0Ch) XReg
Lower Mask of Last Message (EF0Eh/EE0Eh) XReg
15.5 - The Message Object
The message object is the primary means of
communication between CPU and CAN controller.
Each of the 15 message objects uses 15
consecutive bytes (see Figure 64) and starts at an
address that is a multiple of 16.
Note All message objects must be initialized by
Each element of the Message Control Register is
made of two complementary bits.
This special mechanism allows the selective
setting or resetting of specific elements (leaving
others
read-modify-write cycles. None of these elements
will be affected by reset.
Table 29 : Functions of Complementary Bit of Message Control Register
124/186
15
15
15
ID28...0
ID28...0
Bit
ID20...18
the CPU, even those which are not going to
be used, before clearing the INIT bit.
Bit
RW
14
14
14
unchanged)
ID4...0
ID4...0
Identifier (29 bit)
Mask to filter the last incoming message (Nr. 15) with standard or extended identifier (as configured).
RW
RW
Value
13
13
13
00
01
10
11
Identifier (29 bit)
Mask to filter incoming messages with extended identifier.
12
12
12
11
11
11
without
ID17...13
RW
10
10
10
R
R
0
0
Reserved
Reset element
Set element
Leave element unchanged
requiring
R
R
9
0
9
9
0
Function on Write
R
R
8
0
8
8
0
XReg
Function
The Table 29 shows how to use and to interpret
these 2 bit-fields.
Figure 64 : Message Object Address Map
7
7
7
Function
6
6
6
Reserved
Data0
Data2
Data4
Data6
5
5
5
Message Control
Reserved
Element is reset
Element is set
Reserved
Arbitration
ID28...21
4
4
4
ID12...5
ID12...5
Object Start Address
RW
RW
RW
Meaning on Read
Message Config.
3
3
3
Reset Value: UUUUh
Reset Value: UUUUh
Reset Value: UUUUh
Data1
Data3
Data5
Data7
2
2
2
1
1
1
+10
+12
+14
+0
+2
+4
+6
+8
0
0
0