ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 129

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17 - SYSTEM RESET
Table 32 : Reset Event Definition
System reset initializes the MCU in a predefined
state. There are five ways to activate a reset state.
The system start-up configuration is different for
each case as shown in Table 32.
17.1 - Asynchronous Reset (Long Hardware Reset)
An asynchronous reset is triggered when RSTIN pin
is pulled low while RPD pin is at low level. Then the
MCU is immediately forced in reset default state. It
pulls low RSTOUT pin, it cancels pending internal
hold states if any, it waits for any internal access
cycles to finish, it aborts external bus cycle, it
switches buses (data, address and control signals)
and I/O pin drivers to high-impedance, it pulls high
PORT0 pins and the reset sequence starts.
Power-on reset
The asynchronous reset must be used during the
power-on of the MCU. Depending on crystal fre-
quency, the on-chip oscillator needs about 10ms to
50ms to stabilize. The logic of the MCU does not
need a stabilized clock signal to detect an asyn-
chronous reset, so it is suitable for power-on condi-
Figure 65 : Asynchronous Reset Timing
Note: 1. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
Power-on reset
Long Hardware reset (synchronous & asynchronous)
Short Hardware reset (synchronous reset)
Watchdog Timer reset
Software reset
(f
CPU
= f
CPU Clock
RSTIN
RPD
RSTOUT
ALE
PORT0
Internal
Reset
Signal
XTAL
/ 2), else it is 4 CPU clock cycles (8 TCL) .
Reset Source
Reset Condition
Asynchronous
Reset Configuration
6 TCL or 8 TCL
1
Latching point of PORT0
for system start-up
configuration
tions. To ensure a proper reset sequence, the
RSTIN pin and the RPD pin must be held at low
level until the MCU clock signal is stabilized and the
system configuration value on PORT0 is settled.
Hardware reset
The asynchronous reset must be used to recover
from catastrophic situations of the application. It
may be triggerred by the hardware of the applica-
tion. Internal hardware logic and application cir-
cuitry are described in Reset circuitry chapter and
Figures Figure 68 :, Figure 69 : and Figure 70 :.
Exit of asynchronous reset state
When the RSTIN pin is pulled high, the MCU
restarts. The system configuration is latched from
PORT0 and ALE, RD and R/W pins are driven to
their inactive level. The MCU starts program
execution from memory location 00'0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Timing of
asynchronous reset sequence are summarized in
Figure 65.
Short-cut
SHWR
WDTR
PONR
LHWR
SWR
Power-on
t
4 TCL < t
WDT overflow
SRST execution
RSTIN
INST #1
> 1032 TCL
Conditions
RSTIN
< 1032 TCL
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