D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 1074
![IC H8S MCU ROMLESS 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
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Appendix B Internal I/O Registers
TSTR—Timer Start Register
TSYR—Timer Synchro Register
Rev.7.00 Feb. 14, 2007 page 1040 of 1108
REJ09B0089-0700
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Note:
If 0 is written to the CST bit during operation with the TIOC pin designated for output,
the counter stops but the TIOC pin output compare output level is retained. If TIOR is
written to when the CST bit is cleared to 0, the pin output level will be changed to the
set initial output value.
:
:
:
:
:
:
Notes:
⎯
⎯
⎯
⎯
7
0
7
0
1.
2.
To set synchronous operation, the SYNC bits for at least two channels must
be set to 1.
To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing
source must also be set by means of bits CCLR2 to CCLR0 in TCR.
⎯
⎯
⎯
⎯
6
0
6
0
SYNC5
Timer Synchronization
CST5
R/W
R/W
0
1
5
0
5
0
TCNTn operates independently (TCNT presetting/
clearing is unrelated to other channels)
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing
is possible
SYNC4
CST4
R/W
R/W
4
0
4
0
SYNC3
H'FFC0
H'FFC1
Counter Start
R/W
CST3
R/W
3
0
0
1
3
0
TCNTn count operation is stopped
TCNTn performs count operation
SYNC2
R/W
CST2
R/W
2
0
2
0
SYNC1
R/W
CST1
1
0
R/W
1
0
(n = 5 to 0)
SYNC0
R/W
CST0
0
0
R/W
(n = 5 to 0)
0
0
TPU
TPU
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