D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 628
![IC H8S MCU ROMLESS 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
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Section 17 ROM
Notes on Use of Boot Mode
• When the chip comes out of reset in boot mode, it measures the low-level period of the input at
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD1 and TxD1 pins should be pulled up on the board.
• Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF),
Rev.7.00 Feb. 14, 2007 page 594 of 1108
REJ09B0089-0700
Notes: 1. This is a reserved area used only in boot mode. It should not be used for any purpose
the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes
approximately 100 states before the chip is ready to measure the low-level period of the RxD1
pin.
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing
the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The
transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
2. This area cannot be used until a transition is made to the execution state for the
other than flash memory programming/erasing.
programming control program transferred to RAM. Note also that the boot program
remains in this area in RAM even after control branches to the programming control
program.
Figure 17.13 RAM Areas in Boot Mode
H'FFDC00
H'FFE3FF
H'FFEBFF
H'FFEC00
H'FFFBFF
area (2 kbytes)
control program
area (6 kbytes)
Boot program
Programming
*2
Reserved area used
only in boot mode
(4 kbytes)
*1
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