D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 207
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
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6.6
6.6.1
When the chip accesses external space, it can insert a 1-state idle cycle (T
the following two cases: (1) when read accesses in different areas occur consecutively, and (2)
when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible,
for example, to avoid data collisions between ROM, with a long output floating time, and high-
speed memory, I/O interfaces, and so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is
enabled in advanced mode.
Figure 6.16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Address bus
CS (area A)
CS (area B)
Data bus
RD
Idle Cycle
Operation
φ
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
Figure 6.16 Example of Idle Cycle Operation (1)
2
T
Long output
floating time
3
Bus cycle B
T
1
T
2
Data
collision
Address bus
CS (area A)
CS (area B)
Data bus
Rev.7.00 Feb. 14, 2007 page 173 of 1108
RD
φ
T
1
(b) Idle cycle inserted
Bus cycle A
(ICIS1 = 1 (initial value))
T
2
Section 6 Bus Controller
I
) between bus cycles in
T
3
REJ09B0089-0700
T
Bus cycle B
I
T
1
T
2
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