D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 254

• Manufacturer Part Number: D12312SVTEBL25
• Description: IC H8S MCU ROMLESS 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTEBL25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTEBL25; HD6412312SVTEBL25

Section 8 I/O Ports
Rev.7.00 Feb. 14, 2007 page 220 of 1108
REJ09B0089-0700
Port E • 8-bit I/O port
Port F • 8-bit I/O port
Port
• Built-in MOS
• Schmitt-
input pull-up
triggered input
(IRQ3 to IRQ0)
Description
PE7/D7 to PE0/D0
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/IRQ3
PF2/WAIT/IRQ2/BREQO When WAITE = 0, BRLE = 0, BREQOE =
PF1/BACK/IRQ1/CS5
PF0/BREQ/IRQ0/CS4
Pins
In 8-bit bus mode: I/O port
In 16-bit bus mode: data bus input/output
When DDR = 0: input port
When DDR = 1 (after reset):
φ output
When ASOD = 1: I/O port
When ASOD = 0: AS output
RD, HWR output
In 8-bit bus mode: When LWROD = 1, I/O
port
In 16-bit bus mode: LWR output also
functioning as interrupt input pin (IRQ3)
0 (after reset): I/O port also functioning as
interrupt input pin (IRQ2)
When WAITE = 1: WAIT input also
functioning as interrupt input pin (IRQ2)
When WAITE = 0, BRLE = 1, BREQOE =
1: BREQO output also functioning as
interrupt input pin (IRQ2)
When BRLE = 0 (after reset): I/O port also
functioning as interrupt input pins (IRQ1,
IRQ0)
When CS25E = 1, PF1CS5S = 1, and
DDR = 1: Also functions as CS5 output
When CS25E = 1, PF0CS4S = 1, and
DDR = 1: Also functions as CS4 output
When BRLE = 1: BREQ input, BACK
output also functioning as interrupt input
pins (IRQ1, IRQ0)
Mode
4
Mode
5
Mode
6 *
1
I/O port
When DDR =
0 (after
reset): input
port
When DDR =
1: φ output
I/O port
I/O port also
functioning
as interrupt
input pins
(IRQ3 to
IRQ0)
Mode
7 *
1