R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 104

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
11. Protection
Protection function protects important registers from being easily overwritten when a program runs out of control.
Figure 11.1 shows the PRCR Register. The following lists the registers protected by the PRCR register.
Figure 11.1
Protect Register
• Registers protected by PRC0 bit: CM0, CM1, OCD, FRA0, FRA1 and FRA2 registers
• Registers protected by PRC1 bit: PM0 and PM1 registers
• Registers protected by PRC2 bit: PD0 register
• Registers protected by PRC3 bit: VCA2, VW1C and VW2C registers
b7 b6 b5 b4 b3 b2 b1 b0
NOTE:
1. This bit is set to 0 after w riting 1 to the PRC2 bit and executing w riting to any address.
0 0
Since the other bits are not set to 0, set to 0 by a program.
PRCR Register
Bit Symbol
(b5-b4)
(b7-b6)
Symbol
PRCR
PRC0
PRC1
PRC2
PRC3
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—
—
Protect bit 0
Protect bit 1
Protect bit 2
Protect bit 3
Reserved bits
Reserved bits
Address
Bit Name
000Ah
Writing to the CM0, CM, OCD, FRA0, FRA1 and
FRA2 registers is enabled
0 : Disables w riting
1 : Enables w riting
Writing to the PM0 and PM1 registers is enabled
0 : Disables w riting
1 : Enables w riting
Writing to the PD0 register is enabled
0 : Disables w riting
1 : Enables w riting
Writing to the VCA2, VW1C and VW2C registers is
enabled
0 : Disables w riting
1 : Enables w riting
Set to 0
When read, the content is 0.
(1)
After Reset
Function
00h
11. Protection
RW
RW
RW
RW
RW
RW
RO