R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 490

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
1.00
REVISION HISTORY
Nov 15, 2006
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10.4.1.3 Low-Speed On-Chip Oscillator Mode;
mode, setting the VCA20 bit in the VCA2 register to 1 (internal power low
consumption enabled) enables lower consumption current in wait mode.” added.
10.4.2.4 Exiting Wait Mode;
to Interrupt Routine Execution. added.
Figure 10.9 Time from Wait Mode to Interrupt Routine Execution revised.
10.4.2.5 Reducing Internal Power Consumption and Figure 10.10 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit added
10.4.3.3 Exiting Stop Mode, on the 4th line;
Figure 10.11 Time from Stop Mode to Interrupt Routine Execution added.
“Figure 10.10 State Transitions in Power Control Mode” →
10.5.1 How to Use Oscillation Stop Detection Function, on the 6th line;
“Figure 10.11 ~” → “Figure 10.13 ~” corrected.
“Figure 10.12 ~” → “Figure 10.15 ~” corrected.
“10.6 Notes on Clock Generation Circuit” revised.
Figure 12.5 Registers INT0IC to INT3IC;
Figure 12.13 INTF Register revised
Figure 13.2 Registers OFS and WDC;
Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode
Enabled);
Figure 14.1 Block Diagram of Timer RA revised.
Figure 14.2 Registers TRACR and TRAIOC revised.
Figure 14.3 Registers TRAMR and TRAPRE
Figure 14.4 TRA Register;
Table 14.2 Timer Mode Specifications;
“Write to Timer” revised.
Figure 14.5 TRAIOC Register in Timer Mode;
On the 2nd line from the bottom; “To enter wait mode from low-speed clock
On the 13th line from the bottom; Figure 10.9 shows the Time from Wait Mode
“Figure 10.11 shows the Time from Stop Mode to Interrupt Routine Execution.”
“Figure 10.12” → “Figure 10.14” corrected.
On the 10th line; “Figure 10.11” → “Figure 10.13” corrected.
NOTE3; “INTOPL” → “INTiPL” corrected.
Option Function Select Register
Watchdog Timer Control Register revised.
NOTE2; “CSPRO” → “CSPROINI” corrected.
Timer RA Mode Register
Timer RA Prescaler Register; NOTE1 revised.
NOTE1 revised.
NOTES deleted.
“Figure 10.12 State Transitions in Power Control Mode” corrected.
R8C/20 Group, R8C/21 Group Hardware Manual
added.
C - 14
(1)
; NOTE added.
Description
(1)
Summary
; NOTE2 revised.