R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 232

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Table 14.29
j = either A, B, C or D
Count Sources
Count Operations
PWM Waveform
Count Start Condition
Count Stop Conditions
Interrupt Request Generation
Timing
TRDIOA0 Pin Function
TRDIOB0 Pin Function
TRDIOD0 Pin Function
TRDIOA1 Pin Function
TRDIOC1 Pin Function
TRDIOB1 Pin Function
TRDIOD1 Pin Function
TRDIOC0 Pin Function
INT0 Pin Function
Read from Timer
Write to Timer
Selection Functions
Reset Synchronous PWM Mode Specifications
Item
Page 214 of 458
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
The TRD0 register is incremented (The TRD1 register is not used.)
PWM period:
Active level width of normal-phase: 1/fk × (m - n)
Active level width of counter-phase:1/fk × (n + 1)
Write 1 (count starts) to the TSTART0 bit in the TRDSTR register.
• Write 0 (count stops) to the TSTART0 bit in the TRDSTR register
• The PWM output pin holds output level before the count stops
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
• The PWM output pin holds level after output change by the compare
• Compare match (the content in the TRD0 register matches with the
• The TRD0 register overflows
Programmable I/O port or TRDCLK (external clock) input
PWM output 1 normal-phase output
PWM output 1 counter-phase output
PWM output 2 normal-phase output
PWM output 2 counter-phase output
PWM output 3 normal-phase output
PWM output 3 counter-phase output
Output inverted every period of PWM
Programmable I/O port, pulse output forced cutoff signal input or INT0
interrupt input
The count value can be read by reading the TRD0 register.
The value can be written to the TRD0 register.
• The active level of normal-phase and counter-phase and initial
• Buffer operation (refer to 14.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (refer to 14.3.4 Pulse Output
fk:Frequency of count source
m:Setting value in the TRDGRA0 register
n: Setting value in the TRDGRB0 register (PWM output 1),
when the CSEL0 bit in the TRDSTR register is set to 1.
stops at the compare match in the TRDGRA0 register.
match.
content in the TRDGRj0, TRDGRA1 and TRDGRB1 registers.)
output level selected individually.
Forced Cutoff.)
Counter-phase
Normal-phase
Setting value in the TRDGRA1 register (PWM output 2),
Setting value in the TRDGRB1 register (PWM output 3)
n + 1
m + 1
Specification
m - n
1/fk × (m + 1)
(When “L” is selected for the active level)
14. Timers