R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 81

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
9.
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/20 Group and Table 9.2 lists Bus Cycles by Access Space of
the R8C/21 Group.
The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word-(16 bits) unit, these
area are accessed twice in 8-bit unit.
Table 9.3 lists Access Unit and Bus Operations.
However, only following SFRs are connected with the 16-bit bus:
Timer RD: registers TRDi (i = 0, 1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi
Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, data flash, even address
byte access” in Table 9.3 Access Unit and Bus Operations, and 16-bit data is accessed at a time.
Table 9.1
Table 9.2
Table 9.3
SFR
ROM/RAM
SFR/Data flash
Program ROM/RAM
Bus
Even address
Even address
Odd address
word access
word access
byte access
Odd address
byte access
Access Area
Access Area
Area
Access Unit and Bus Operations
Bus Cycles by Access Space of the R8C/20 Group
Bus Cycles by Access Space of the R8C/21 Group
CPU clock
CPU clock
CPU clock
CPU clock
Address
Address
Address
Address
Data
Data
Data
Data
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2 cycles of CPU clock
1 cycle of CPU clock
2 cycles of CPU clock
1 cycle of CPU clock
SFR, data flash
Odd
Even
Bus Cycle
Bus Cycle
Data
Data
Even
Odd
Even + 1
Odd + 1
Data
Data
Data
Data
CPU clock
CPU clock
CPU clock
CPU clock
Address
Address
Address
Address
Data
Data
Data
Data
ROM (program ROM), RAM
Odd
Even
Odd
Even
Data
Data
Data
Data
Even + 1
Odd + 1
Data
Data
9. Bus