R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 459

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 21.6
•
Select with the CMD1 to CMD0 bits for the data transfer timing from the buffer register to the general
register. However, transfer with the following timing in spite of the value of the CMD1 to CMD0 bits for
the following cases:
Value in buffer register ≥ Value in TRDGRA0 register:
Transfer at the underflow in the TRD1 register.
And then, when setting the buffer register to 0001h or above and the smaller value than the one in the
TRDGRA0 register, and the TRD1 register underflows in the fist time after setting, the value is transferred
to the general register. After that, transfer the value with the timing selected by the CMD1 to CMD0 bits.
TRDGRD0 register
TRDGRB0 register
TRDIOD0 output
TRDIOB0 output
Operation When Value in Buffer Register ≥ Value in TRDGRA0 Register in
Complementary PWM Mode
The above applies to the following conditions:
• The CMD1 to CMD0 bits in the TRDFCR register are set to 11b.
• Both the OSL0 and OLS1 bits in the TRDFCR are set to 1. (active ‘H” for normal-phase and counter-phase)
(Data in the buffer register is transferred at the compare match in the TRD0 and TRDGRA0 registers in complementary
PWM mode.)
Transfer with timing set by
CMD1 to CMD0 bits
m + 1
0000h
n3
n2
n1
Page 441 of 458
Transfer
n2
n1
n2
Transfer by
underflow in TRD1
register because of
n3 > m
n3
Transfer
n3
Transfer by
underflow in TRD1
register because
of first setting to
n2 < m
Transfer
n2
m: Setting Value in TRDGRA0 Register
n2
n1
Transfer with timing set by
CMD1 to CMD0 bits
Transfer
n1
Count value in TRD0
register
Count value in TRD1
register
21. Usage Notes