R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 234

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.78
Timer RD Mode Register
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2
b7 b6 b5 b4
NOTES:
1.
2.
3. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or
complementary PWM mode in spite of the setting of the TRDPMR register.
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops).
enabled.
b3 b2
b1 b0
Registers TRDMR and TRDFCR in Reset Synchronous PWM Mode
b1 b0
0 1
0
Bit Symbol
Bit Symbol
(b3 - b1)
TRDFCR
ADTRG
Symbol
TRDMR
Symbol
STCLK
SYNC
ADEG
PWM3
CMD0
CMD1
OLS0
OLS1
BFC0
BFD0
BFC1
BFD1
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Timer RD synchronous bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRDGRC0 register function
selection bit
TRDGRD0 register function
selection bit
TRDGRC1 register function
selection bit
TRDGRD1 register function
selection bit
Combination mode selection bit
Normal-phase output level selection
bit (in reset synchronous PWM mode
or complementary PWM mode)
Counter-phase output level selection
bit (in reset synchronous PWM mode
or complementary PWM mode)
A/D trigger enable bit
(in complementary PWM mode)
A/D trigger edge selection bit
(in complementary PWM mode)
External clock input selection bit
PWM3 mode selection bit
Address
Bit Name
0138h
Address
Bit Name
013Ah
(3)
(1,2)
Set this bit to 0 (the TRD and TRD1 registers
operate independently.) in reset synchronous
PWM mode.
0 : General register
1 : Buffer register of TRDGRA0 register
0 : General register
1 : Buffer register of TRDGRB0 register
0 : General register
1 : Buffer register of TRDGRA1 register
0 : General register
1 : Buffer register of TRDGRB1 register
Set to 01b (reset synchronous PWM
mode) in reset synchronous PWM mode.
0 : Initial output “H”
1 : Initial output “L”
0 : Initial output “H”
1 : Initial output “L”
This bit is disabled in reset synchronous
PWM mode.
This bit is disabled in reset synchronous
PWM mode.
0 : External clock input disabled
1 : External clock input enabled
This bit is disabled in reset synchronous
PWM mode.
Active level “L”
Active level “H”
Active level “L”
Active level “H”
After Reset
00001110b
Function
After Reset
10000000b
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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