R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 330

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
16.3
Table 16.5
NOTE:
Communication
Formats
I/O Pins
Transfer Clocks
Receive Error Detection • Detects overrun error (clock synchronous serial format)
Interrupt Sources
Select Functions
The I
Philips I
Table 16.5 lists a I
Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.24 to 16.31 show
the registers associated with the I
* I
1. The interrupt sources can use the only I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
2
I
C bus interface is the circuit which is used for a serial communication based on the data transfer format of the
2
2
C Bus Interface
C bus.
Item
I
2
C Bus Interface Specifications
2
C bus Interface Specifications, Figure 16.22 shows a Block Diagram of I
Page 312 of 458
• I
• Clock synchronous serial format
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
• When the MST bit in the ICCR1 register is set to 0
• When the MST bit in the ICCR1 register is set to 1
• I
• Clock synchronous serial format ...... 4 types
• I
• Clock synchronous serial format
2
- Selectable for master / slave device
- Continuous transmit / receive (since the shift register, transmit data register
- Start / stop conditions are automatically generated in master mode
- Automatic loading of acknowledge bit when transmit
- Bit synchronization / wait function (in master mode, the state of the SCL
- Direct drive of the SCL and SDA pins (N-channel open drain output) is
- Continuous transmit / receive (since the shift register, transmit data register
The external clock (input from the SCL pin)
The internal clock selected by the CKS0 to CKS3 bits in the ICCR1 register
(output from the SCL pin)
An overrun error occurs during receive. When the last bit of the following data
is received while the RDRF bit in the ICSR register is set to 1 (data in the
ICDRR register), the AL bit is set to 1.
2
Transmit data empty (including when slave address matches), transmit ends,
receive data full (including when slave address matches), arbitration lost,
NACK detection and stop condition detection.
Transmit data empty, transmit ends, receive data full and overrun error
2
- Selectable for the output level of the acknowledge signal when receive
- Selectable for the MSB-first or LSB-first to the data transfer direction
C bus format
C bus format .................................. 6 types
C bus format
and receive data register are independent)
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, stand by to set the SCL signal to “L”.
enabled
and receive data register are independent)
2
C bus interface.
2
C bus interface interrupt vector table.
Specification
16. Clock Synchronous Serial Interface
(1)
(1)
2
C bus Interface and