R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 215

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.60
TRDSTR register
TRDSRi register
TRDSRi register
TRDSRi register
TRDIOCi output
TRDIOBi output
TRDIOAi output
TSTARTi bit in
The above applies to the following conditions:
The CSELi bit in the TRDSTR register is set to 1. (The TRDi register is not stopped by the compare match.)
The BFCi and BFDi bits in the TRDMR register are set to 0. (The TRDGRCi and TRDGRDi registers are not used as the buffer register.)
The EAi, EBi and ECi bits in the TRDOER1 register are set to 0. (Enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs.)
The CCLR2 to CCLR0 bits in the TRDCRi register are set to 001b. (Set the TRDi register to 000h by the compare match in the TRDGRAi register.)
The TOAi and TOBi bits in the TRDOCR register is set to 0. (initial output “L” to the compare match), the TOCi bit is set to 1. (initial output “H” to the compare match.)
The IOA2 to IOA0 bits in the TRDIORAi register are set to 011b. (TRDIOAi output inversed at the TRDGRAi register compare match.)
The IOB2 to IOB0 bits in the TRDIORAi register are set to 010b. (TRDIOBi “H” output at the TRDGRBi register compare match.)
The IOC3 to IOC0 bits in the TRDIORCi register are set to 1001b. (TRDIOCi “L” output at the TRDGRCi register compare match.)
The IOD3 bit in the TRDIORCi register is set to 1. (TRDGRDi register does not control TRDIOBi pin output.)
i = 0 or 1
IMFC bit in
IMFA bit in
IMFB bit in
Count source
Value in TRDi register
1
0
1
0
1
0
1
0
Operating Example of Output Compare Function
m
m
n
n
p
p
Initial output “H”
Page 197 of 458
Initial output “L”
P + 1
Initial output “L”
n + 1
n + 1
m + 1
“L” output by compare match
m: Setting value in TRDGRAi register
n: Setting value in TRDGRBi register
p: Setting value in TRDGRCi register
Set to “0” by a program
“H” output by compare match
Set to 0 by a program
Output inversed by compare match
Set to 0 by a program
m + 1
Count
stop
Output level
Output level
Output level
held
held
held
restarts
Count
14. Timers