R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 416
R5F21217JFP#U1
Manufacturer Part Number
R5F21217JFP#U1
Description
MCU FLASH 48K 2.5K CMOS 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/21r
Datasheet
1.R5F21216JFP.pdf
(503 pages)
Specifications of R5F21217JFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21217JFP#U1R5F21217JFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
19.4.5
Table 19.6
NOTE:
FMR07(SR5) FMR06(SR4)
1. The MCU enters read array mode by writing FFh in the second bus cycle of these commands, at the
FMR0 Register (Status
When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to 1, indicating occurrence of
each specific error. Therefore, checking these status bits (full status check) can determine the executed result.
Table 19.6 lists the Errors and FMR0 Register Status. Figure 19.16 shows the Full Status Check and Handling
Procedure for Individual Errors.
same time the command code written in the first bus cycle will disabled.
1
1
0
Register) Status
Full Status Check
Errors and FMR0 Register Status
1
0
1
Page 398 of 458
Command
sequence
error
Erase error
Program error
Error
• When the program command is executed but not
• When any command is not written correctly
• When invalid data other than those that can be written
• When executing the program command or block erase
• When inputting and erasing the address in which the
• When executing to erase the block which disables
• When inputting and writing the address in which the
• When executing to write the block which disables
• When the block erase command is executed but not
in the second bus cycle of the block erase command is
written (i.e., other than D0h or FFh)
command while rewriting is disabled using the FMR02
bit in the FMR0 register, the FMR15 or FMR16 bit in the
FMR1 register.
Flash memory is not allocated during the erase
command input
rewriting during the erase command input.
Flash memory is not allocated during the write
command input.
rewriting during the write command input.
automatically erased correctly
automatically programmed correctly.
Error Occurrence Condition
(1)
19. Flash Memory
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