R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 263

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.105 Registers TRDIER0 and TRDIER1 in PWM3 Mode
Figure 14.106 TRD0 Register in PWM3 Mode
Timer RD Interrupt Enable Register i (i = 0 or 1)
Timer RD Counter 0
(b15)
b7 b6 b5 b4
b7
NOTES:
1.
2.
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
The TRD1 register is not used in PWM3 mode.
b3 b2
b1 b0
(b8)
b0
b7
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
(1,2)
Bit Symbol
TRDIER0
TRDIER1
(b7 - b5)
Symbol
IMIEA
IMIEB
IMIEC
IMIED
OVIE
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—
Input capture/compare match
interrupt enable bit A
Input capture/compare match
interrupt enable bit B
Input capture/compare match
interrupt enable bit C
Input capture/compare match
interrupt enable bit D
Overflow /underflow interrupt enable
bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
b0
Symbol
TRD0
Address
Bit Name
0144h
0154h
Function
0147h-0146h
Address
0 : Disable an interrupt (IMIA) by the
1 : Enable an interrupt (IMIA) by the
0 : Disable an interrupt (IMIB) by the
1 : Enable an interrupt (IMIB) by the
0 : Disable an interrupt (IMIC) by the
1 : Enable an interrupt (IMIC) by the
0 : Disable an interrupt (IMID) by the
1 : Enable an interrupt (IMID) by the
0 : Disable an interrupt (OVI) by the
1 : Enable an interrupt (OVI) by the
IMFA bit
IMFA bit
IMFB bit
IMFB bit
IMFC bit
IMFC bit
IMFD bit
IMFD bit
OVF bit
OVF bit
After Reset
11100000b
11100000b
Function
0000h to FFFFh
Setting Range
After Reset
0000h
14. Timers
RW
RW
RW
RW
RW
RW
—
RW
RW