R5F21217JFP#U1 Renesas Electronics America, R5F21217JFP#U1 Datasheet - Page 370

• Manufacturer Part Number: R5F21217JFP#U1
• Description: MCU FLASH 48K 2.5K CMOS 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 17.7
17.4.2
IR bit in the TRAIC
RXDSF flag in the
SBDCT flag in the
SFDCT flag in the
Figure 17.7 shows a Typical Operation when Receiving a Header Field. Figure 17.8 through Figure 17.10 show
an Example of Header Field Reception Flowchart.
When receiving a header field, the hardware LIN operates as described below.
LINCR register
RXD0 input for
LINST register
LINST register
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware
(2) When a low-level signal is input for a duration equal to or greater than the period set in timer RA, the
(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and
(4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finished measuring the Synch
(5) After it finished measuring the Synch Field, the hardware LIN calculates a transfer rate from the count
(6) The hardware LIN performs communication for a response field after it finished receiving the ID field.
RXD0 pin
Slave Mode
• When LINE bit = 1 (Causes LIN to start operating), MST bit = 0 (Slave mode), SBIE bit = 1
LIN.
hardware LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA
interrupt. Then it goes to Synch Field measurement.
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal
to RxD0 of UART0 by setting the SBE bit in the LINCR register accordingly.
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.
value of timer RA and sets the result in UART0 and sets the TRAPRE and TRA registers of the timer
RA back again. Then it receives an ID field via UART0.
register
UART0
(Enables Synch Break detection interrupt), SFIE bit = 1 (Enables Synch Field measurement
completed interrupt)
Typical Operation when Receiving a Header Field
1
0
1
0
1
0
1
0
1
0
1
0
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(1)
Set by writing 1 to
the LSTART bit in
the LINCR register
Synch Break
(2)
(3)
Measure this period
Set by writing 1 to
the B1CLR bit in
the LINST register
Cleared to 0 upon
acceptance of
interrupt request or
by a program
Synch Field
(4)
(5)
Set by writing 1 to the
B0CLR bit in the LINST
register
Cleared to 0 when Synch
Field measurement
finishes
IDENTIFIER
17. Hardware LIN
(6)